? 2005 fairchild semiconductor corporation ds009958 www.fairchildsemi.com november 1988 revised march 2005 74ac373 ? 74act373 octal transparent latch with 3-state outputs 74ac373 74act373 octal transparent latch with 3-state outputs general description the ac/act373 consists of eight latches with 3-state outputs for bus organized system applications. the flip- flops appear transparent to the data when latch enable (le) is high. when le is low, the data that meets the setup time is latched. data appears on the bus when the output enable (oe ) is low. when oe is high, the bus output is in the high impedance state. features i cc and i oz reduced by 50% eight latches in a single package 3-state outputs for bus interfacing outputs source/sink 24 ma act373 has ttl-compatible inputs ordering code: device also available in tape and reel. specify by appending suffix letter ?x? to the ordering information. pb-free package per jedec j-std-020b. note 1: ?_nl? indicated pb-free package (per jedec j-std-020b). device available in tape and reel only. fact is a trademark of fairchild semiconductor corporation. order number package package description number 74ac373sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74ac373sj m20d pb-free 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74ac373mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74ac373pc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide 74act373sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74act373scx_nl (note 1) m20b pb-free 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74act373sj m20d pb-free 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74act373msa msa20 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide 74act373mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act373mtcx_nl (note 1) mtc20 pb-free 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act373pc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
www.fairchildsemi.com 2 74ac373 74act373 logic symbols ieee/iec connection diagram pin descriptions truth table h high voltage level l low voltage level z high impedance x immaterial o 0 previous o 0 before high-to-low transition of latch enable functional description the ac/act373 contains eight d-type latches with 3- state standard outputs. when the latch enable (le) input is high, data on the d n inputs enters the latches. in this condition the latches are transparent, i.e., a latch out- put will change state each time its d-type input changes. when le is low, the latches store the information that was present on the d-type inputs a setup time preceding the high-to-low transition of le. the 3-state standard outputs are controlled by the output enable (oe ) input. when oe is low, the standard outputs are in the 2-state mode. when oe is high, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. pin names description d 0 ? d 7 data inputs le latch enable input oe output enable input o 0 ? o 7 3-state latch outputs inputs outputs le oe d n o n xhx z hll l hlh h llx o 0
3 www.fairchildsemi.com 74ac373 74act373 absolute maximum ratings (note 2) recommended operating conditions note 2: absolute maximum ratings are those values beyond which damage to the device may occur. the databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. fairchild does not recommend operation of fact circuits outside databook specifications. dc electrical characteristics for ac note 3: all outputs loaded, thresholds on input associated with output under test. note 4: maximum test duration 2.0 ms, one output loaded at a time. note 5: i in and i cc @ 3.0v are guaranteed to be less than or equal to the respective limit @ 5.5v v cc . supply voltage (v cc ) 0.5v to 7.0v dc input diode current (i ik ) v i 0.5v 20 ma v i v cc 0.5v 20 ma dc input voltage (v i ) 0.5v to v cc 0.5v dc output diode current (i ok ) v o 0.5v 20 ma v o v cc 0.5v 20 ma dc output voltage (v o ) 0.5v to v cc 0.5v dc output source or sink current (i o ) r 50 ma dc v cc or ground current per output pin (i cc or i gnd ) r 50 ma storage temperature (t stg ) 65 q c to 150 q c junction temperature (t j ) pdip 140 q c supply voltage (v cc ) ac 2.0v to 6.0v act 4.5v to 5.5v input voltage (v i )0v to v cc output voltage (v o )0v to v cc operating temperature (t a ) 40 q c to 85 q c minimum input edge rate ( ' v/ ' t) ac devices v in from 30% to 70% of v cc v cc @ 3.3v, 4.5v, 5.5v 125 mv/ns minimum input edge rate ( ' v/ ' t) act devices v in from 0.8v to 2.0v v cc @ 4.5v, 5.5v 125 mv/ns symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units conditions (v) typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out 0.1v input voltage 4.5 2.25 3.15 3.15 v or v cc 0.1v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out 0.1v input voltage 4.5 2.25 1.35 1.35 v or v cc 0.1v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 output voltage 4.5 4.49 4.4 4.4 v i out 50 p a 5.5 5.49 5.4 5.4 v in v il or v ih 3.0 2.56 2.46 i oh 12 ma 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 i ol 24 ma (note 3) v ol maximum low level 3.0 0.002 0.1 0.1 output voltage 4.5 0.001 0.1 0.1 v i out 50 p a 5.5 0.001 0.1 0.1 v in v il or v ih 3.0 0.36 0.44 i ol 12 ma 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 i ol 24 ma (note 3) i in (note 5) maximum input leakage current 5.5 r 0.1 r 1.0 p av i v cc , gnd i oz maximum 3-state current v i (oe) v il , v ih 5.5 r 0.25 r 2.5 p av i v cc , gnd v o v cc , gnd i old minimum dynamic output current (note 4) 5.5 75 ma v old 1.65v max i ohd 5.5 75 ma v ohd 3.85v min i cc (note 5) maximum quiescent supply current 5.5 4.0 40.0 p av in v cc or gnd
www.fairchildsemi.com 4 74ac373 74act373 dc electrical characteristics for act note 6: all outputs loaded; thresholds on input associated with output under test. note 7: maximum test duration 2.0 ms, one output loaded at a time. ac electrical characteristics for ac note 8: voltage range 3.3 is 3.3v r 0.3v voltage range 5.0 is 5.0v r 0.5v symbol parameter v cc t a 25 q ct a 40 q c to 85 q units conditions (v) typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out 0.1v input voltage 5.5 1.5 2.0 2.0 or v cc 0.1v v il maximum low level 4.5 1.5 0.8 0.8 v v out 0.1v input voltage 5.5 1.5 0.8 0.8 or v cc 0.1v v oh minimum high level 4.5 4.49 4.4 4.4 v i out 50 p a output voltage 5.5 5.49 5.4 5.4 v in v il or v ih 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 i oh 24 ma (note 6) v ol maximum low level 4.5 0.001 0.1 0.1 v i out 50 p a output voltage 5.5 0.001 0.1 0.1 v in v il or v ih 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 i ol 24 ma (note 6) i in maximum input 5.5 r 0.1 r 1.0 p av i v cc , gnd leakage current i oz maximum 3-state 5.5 r 0.25 r 2.5 p a v i v il , v ih current v o v cc , gnd i cct maximum i cc /input 5.5 0.6 1.5 ma v i v cc 2.1v i old minimum dynamic 5.5 75 ma v old 1.65v max i ohd output current (note 7) 5.5 75 ma v ohd 3.85v min i cc maximum quiescent 5.5 4.0 40.0 p a v in v cc supply current or gnd v cc t a 25 q ct a 40 q c to 85 q c symbol parameter (v) c l 50 pf c l 50 pf units (note 8) min typ max min max t plh propagation delay 3.3 1.5 10.0 13.5 1.5 15.0 ns d n to o n 5.0 1.5 7.0 9.5 1.5 10.5 t phl propagation delay 3.3 1.5 9.5 13.0 1.5 14.5 ns d n to o n 5.0 1.5 7.0 9.5 1.5 10.5 t plh propagation delay 3.3 1.5 10.0 13.5 1.5 15.0 ns le to o n 5.0 1.5 7.5 9.5 1.5 10.5 t phl propagation delay 3.3 1.5 9.5 12.5 1.5 14.0 ns le to o n 5.0 1.5 7.0 9.5 1.5 10.5 t pzh output enable time 3.3 1.5 9.0 11.5 1.0 13.0 ns 5.0 1.5 7.0 8.5 1.0 9.5 t pzl output enable time 3.3 1.5 8.5 11.5 1.0 13.0 ns 5.0 1.5 6.5 8.5 1.0 9.5 t phz output disable time 3.3 1.5 10.0 12.5 1.0 14.5 ns 5.0 1.5 8.0 11.0 1.0 12.5 t plz output disable time 3.3 1.5 8.0 11.5 1.0 12.5 ns 5.0 1.5 6.5 8.5 1.0 10.0
5 www.fairchildsemi.com 74ac373 74act373 ac operating requirements for ac note 9: voltage range 3.3 is 3.3v r 0.3v voltage range 5.0 is 5.0v r 0.5v ac electrical characteristics for act note 10: voltage range 5.0 is 5.0v r 0.5v ac operating requirements for act note 11: voltage range 5.0 is 5.0v r 0.5v capacitance v cc t a 25 q ct a 40 q c to 85 q c symbol parameter (v) c l 50 pf c l 50 pf units (note 9) typ guaranteed minimum t s setup time, high or low 3.3 3.5 5.5 6.0 ns d n to le 5.0 2.0 4.0 4.5 t h hold time, high or low 3.3 3.0 1.0 1.0 ns d n to le 5.0 1.5 1.0 1.0 t w le pulse width, 3.3 4.0 5.5 6.0 ns high 5.0 2.0 4.0 4.5 v cc t a 25 q ct a 40 q c to 85 q c symbol parameter (v) c l 50 pf c l 50 pf units (note 10) min typ max min max t plh propagation delay 5.0 2.5 8.5 10.0 1.5 11.5 ns d n to o n t phl propagation delay 5.0 2.0 8.0 10.0 1.5 11.5 ns d n to o n t plh propagation delay 5.0 2.5 8.5 11.0 2.0 11.5 ns le to o n t phl propagation delay 5.0 2.0 8.0 10.0 1.5 11.5 ns le to o n t pzh output enable time 5.0 2.0 8.0 9.5 1.5 10.5 ns t pzl output enable time 5.0 2.0 7.5 9.0 1.5 10.5 ns t phz output disable time 5.0 2.5 9.0 11.0 2.5 12.5 ns t plz output disable time 5.0 1.5 7.5 8.5 1.0 10.0 ns v cc t a 25 q ct a 40 q c to 85 q c symbol parameter (v) c l 50 pf c l 50 pf units (note 11) typ guaranteed minimum t s setup time, high or low 5.0 0.8 2.5 3.5 ns d n to le t h hold time, high or low 5.0 0 0 1.0 ns d n to le t w le pulse width, high 5.0 2.0 7.0 8.0 ns symbol parameter typ units conditions c in input capacitance 4.5 pf v cc open c pd power dissipation capacitance 40.0 pf v cc 5.0v
www.fairchildsemi.com 6 74ac373 74act373 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m20b
7 www.fairchildsemi.com 74ac373 74act373 physical dimensions inches (millimeters) unless otherwise noted (continued) pb-free 20-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m20d
www.fairchildsemi.com 8 74ac373 74act373 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide package number msa20
9 www.fairchildsemi.com 74ac373 74act373 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20
www.fairchildsemi.com 10 74ac373 74act373 octal transparent latch with 3-state outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide package number n20a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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